In this lesson, you will learn how to use the Nested Vectored Interrupt Controller (NVIC) to manually trigger an interrupt from software, allowing you to defer task processing or synchronize asynchronous events.
The Concept of Software Triggers
Normally, interrupts are triggered by external hardware events like a timer overflow or a button press. However, the ARM Cortex-M NVIC includes a dedicated register called the Software Trigger Interrupt Register (STIR). Writing an interrupt ID number to this register forces the processor to treat it as if a hardware interrupt just occurred.
This is incredibly useful for "deferred task processing." If a high-priority routine (like an Interrupt Service Routine) needs to perform a long task but shouldn't stay in the interrupt context for too long, it can "post" a software interrupt to handle that work at a lower priority later.
Implementing the Trigger
To trigger an interrupt in software, you write the desired exception number to the NVIC->STIR register. For example, if you have a user-defined interrupt with an IRQ number of 10, you can trigger it as follows:
#define NVIC_STIR_BASE 0xE000EF00 // Standard address for Cortex-M
#define STIR_REGISTER (*(volatile uint32_t*)NVIC_STIR_BASE)
void trigger_task_sync(uint32_t irq_number) {
// Write the IRQ number to the STIR to pend the interrupt
STIR_REGISTER = irq_number;
}
Why Use This for Synchronization?
Software-triggered interrupts effectively decouple an event from its execution. By triggering a software interrupt, you create a "pending" flag in the NVIC. Because the NVIC manages priorities, you can ensure that this deferred task only executes when the processor is ready to handle that specific priority level. It provides a clean way to signal to your background task scheduler—or a secondary low-priority routine—that data is ready to be processed without needing to check flags constantly in a while loop.
Remember that when you trigger the interrupt manually, the processor will follow the standard exception entry sequence you learned in previous lessons, including automatic context saving and jumping to the address defined in your Vector Table.
Key Takeaway: The STIR register allows software to force the NVIC to pend an interrupt, providing a powerful mechanism to defer processing or synchronize tasks across different priority levels.