Handling DMA Transfer Completion and Error Interrupts

In this lesson, you will learn how to write Interrupt Service Routines (ISRs) to detect when a DMA controller has finished moving data or encountered a critical system error.

When the DMA controller performs a transfer, it doesn't just "fire and forget." It updates internal status registers to let the CPU know what happened. Because the DMA operates independently of the CPU, we rely on interrupts to signal that a transfer block is complete or that a bus error—such as trying to write to read-only memory—has occurred.

Managing Interrupt Status Flags

Every DMA controller has a status register. When an interrupt triggers, your first job inside the ISR is to inspect this register to determine why the interrupt occurred. Usually, there are specific bits for "Transfer Complete" (TC) and "Transfer Error" (TE).

void DMA1_Channel1_IRQHandler(void) {
    // Check the Interrupt Status Register
    uint32_t status = DMA1->ISR;

    if (status & DMA_ISR_TCIF1) {
        // Transfer Success: Clear flag and notify system
        DMA1->IFCR |= DMA_IFCR_CTCIF1; 
        transfer_complete = 1;
    } 
    else if (status & DMA_ISR_TEIF1) {
        // Bus Error: Handle the fault, log, or stop system
        DMA1->IFCR |= DMA_IFCR_CTEIF1;
        handle_dma_error();
    }
}

The Importance of Clearing Flags

A common pitfall in bare-metal programming is forgetting to clear the interrupt flag. If you don't write to the Interrupt Flag Clear Register (IFCR), the DMA controller will think the interrupt is still pending. As soon as you exit the ISR, the hardware will immediately jump back into the same ISR, trapping your processor in an infinite loop.

Always check your hardware reference manual for the specific register bits that clear these signals. A successful transfer is usually just a housekeeping task, but a transfer error is a serious event that typically suggests a memory protection violation or an invalid pointer. Treating these as distinct events allows your system to remain robust even when data movement operations fail.

Key Takeaway: Always inspect status flags upon DMA interrupt entry and explicitly clear them to prevent recursive interrupt triggers, while treating transfer errors as critical system faults.