Designing Power Delivery Networks for Minimum Quiescent Current

Learners will select components and topology configurations to minimize static power consumption in the power delivery path during standby states.

In this lesson, you will learn how to architect your Power Delivery Network (PDN) to minimize quiescent current ( $I_Q$ ) losses during standby states when your system is doing little to no work.

Understanding Quiescent Current in the PDN

While active power management (like clock gating or frequency scaling) dominates during operation, quiescent current is the "background tax" your system pays just by being connected to a power source. In deep sleep or standby, the $I_Q$ of your voltage regulators and the leakage paths through passive components often dictate the battery life of a device.

Selecting the Right Regulator Topology

The first step in minimizing $I_Q$ is selecting the correct regulator for the standby state.

Linear Regulators (LDOs): Choose ultra-low $I_Q$ LDOs (often in the sub-500nA range). They are ideal for low-current standby because they lack the switching noise and high-side driver power consumption associated with DC-DC converters.
Switching Regulators (Buck/Boost): These are excellent for efficiency during high-load operations, but they often have higher quiescent current due to their internal control circuitry. To minimize $I_Q$ , ensure your chosen buck converter features a "Pulse Frequency Modulation" (PFM) or "Burst Mode" that disables internal oscillators during light loads.

Minimizing Leakage Paths

Even with an efficient regulator, the PDN can bleed current through secondary paths.

Feedback Divider Selection: If you are using an adjustable regulator, the feedback resistor string is a constant leakage path. If your feedback resistors are too low (e.g., 10kΩ), you are leaking unnecessary current to ground. Use mega-ohm range resistors where possible to minimize this draw.
Control Pin Management: Ensure that any "Enable" or "Shutdown" pins are tied to a stable reference (either VCC or GND) via a high-impedance path to prevent floating states, which can cause internal regulator logic to oscillate and draw significantly higher current.

// Example: Selecting a low-leakage feedback network
// R1 / R2 should be in the MΩ range to minimize quiescent loss
float V_out = V_ref * (1 + (R1 / R2)); 
// During standby, if the regulator supports a 'shutdown' pin:
set_regulator_shutdown_mode(ENABLE); // Drop I_Q to < 100nA

Key Takeaway: To minimize standby quiescent current, prioritize ultra-low $I_Q$ linear regulators for low-load states and scale your feedback network impedance to suppress unnecessary leakage paths.