Modeling Static Power Dissipation in CMOS

In this lesson, you will learn how to quantify the baseline power draw of idle CMOS circuits by modeling subthreshold conduction and gate-oxide tunneling currents.

As we scale down to modern process nodes, leakage current has become a dominant component of a system's total power budget, even when the clock is gated. Static power dissipation, defined as $P_{static} = V_{dd} \times I_{leak}$, occurs because the transistor is not a perfect switch.

Subthreshold Conduction ($I_{sub}$)

Even when a MOSFET is in the "off" state ($V_{gs} < V_{th}$), a weak inversion layer exists, allowing current to flow from drain to source. This subthreshold current is highly sensitive to the threshold voltage ($V_{th}$) and temperature. We model it using the exponential relationship:

$I_{sub} \propto \exp\left(\frac{V_{gs} - V_{th}}{n \cdot V_T}\right)$

In idle embedded systems, reducing $V_{dd}$ or increasing $V_{th}$ (via body biasing) are common strategies to suppress this exponential leakage.

Gate-Oxide Tunneling ($I_{gate}$)

As gate-oxide layers reach atomic scales (a few nanometers), electrons can "tunnel" directly through the insulating barrier of the transistor gate. Unlike subthreshold leakage, which is controlled by the channel potential, gate tunneling is a quantum mechanical effect that depends on the oxide thickness ($T_{ox}$) and the electric field across the gate.

Modeling for Power Estimation

To calculate the total static power for an idle block, we aggregate the leakage from all gates in the design:

# Simplified static power estimation model
def calculate_static_power(num_gates, v_dd, i_sub, i_gate):
    # Total leakage current per gate
    i_leak_per_gate = i_sub + i_gate
    # Total static power draw
    p_static = v_dd * (num_gates * i_leak_per_gate)
    return p_static

# Example: 1 million gates at 0.8V
power = calculate_static_power(1e6, 0.8, 1e-9, 0.5e-9) 
print(f"Baseline idle power: {power:.4f} Watts")

When analyzing an idle embedded system, these values form the "power floor." If your mission-critical system must operate on a constrained battery budget during deep sleep, these leakage currents represent the minimum energy cost of keeping the logic state alive.

Key Takeaway: Static power dissipation is the summation of subthreshold conduction and gate-oxide tunneling, acting as an unavoidable power floor that must be minimized through process technology and supply voltage management.