Optimizing Power via Dynamic Voltage and Frequency Scaling

In this lesson, you will learn how to coordinate frequency reduction with voltage scaling to exploit the quadratic relationship between supply voltage and dynamic power consumption.

The Physics of Power Savings

As we established in our study of dynamic switching power, the power consumed by CMOS circuits is defined by the relationship: P ∝ C × V² × f

While scaling the clock frequency (f) provides a linear reduction in power, scaling the supply voltage (V) provides a quadratic reduction. However, there is a catch: digital logic circuits require higher voltages to operate at higher frequencies (to ensure signals stabilize within the clock cycle). If you drop the frequency, you can safely lower the voltage while maintaining timing integrity, effectively "buying" a massive reduction in power.

Implementing the Strategy

In practice, you must perform these steps in a specific order to maintain stability. When downscaling, you must decrease the frequency first (to ensure the slower clock speed matches the current voltage’s timing limits) and then decrease the voltage. When upscaling, you must increase the voltage first (to provide the necessary switching speed) before increasing the frequency.

Consider a simplified control loop for a governor:

void set_performance_state(uint32_t target_freq_hz) {
    // 1. Scale down: Reduce frequency first, then voltage
    if (target_freq_hz < current_freq) {
        set_clock_frequency(target_freq_hz);
        set_core_voltage(calculate_min_v(target_freq_hz));
    } 
    // 2. Scale up: Increase voltage first, then frequency
    else {
        set_core_voltage(calculate_min_v(target_freq_hz));
        set_clock_frequency(target_freq_hz);
    }
}

Avoiding Stability Hazards

The critical design constraint is the V-f curve. Every microcontroller has a hardware-defined operating range; attempting to run at a high frequency with a voltage that is too low will result in setup-time violations, leading to non-deterministic data corruption or system crashes. You must ensure your calculate_min_v function strictly follows the silicon manufacturer’s voltage-to-frequency lookup table to ensure the system remains within its defined safety envelope.

Key Takeaway: By lowering the supply voltage alongside frequency, you move from linear power savings to a quadratic reduction, drastically extending battery life while maintaining system timing safety.