In this lesson, you’ll learn how restructuring your data layout minimizes memory bus activity, significantly reducing the energy cost per operation.
In embedded systems, the most power-hungry operations are often those that force the CPU to wait for data from external memory. When the processor requests a piece of data not found in the cache (a cache miss), the memory controller must trigger a high-energy burst across the system bus to fetch an entire cache line. By ensuring your data is laid out contiguously, you increase the likelihood that subsequent data accesses are already waiting in the cache, allowing the CPU to remain in a higher-performance state for less time.
Struct of Arrays vs. Array of Structs
Consider a system processing a stream of sensor readings where each reading consists of a timestamp, value, and status.
If you use an Array of Structs (AoS), memory is laid out like this:
[time1, val1, stat1, time2, val2, stat2, ...]
If your algorithm only needs to calculate the average of all value fields, the CPU must load the entire struct into the cache line just to read the value. This "pollutes" the cache with timestamp and status data you aren’t currently using, forcing the bus to work harder than necessary.
Instead, use a Struct of Arrays (SoA):
struct SensorData {
uint32_t timestamps[N];
float values[N];
uint8_t statuses[N];
};
By separating these into distinct arrays, a request for values[i] brings values[i+1] and values[i+2] into the cache automatically. Because the data is now packed contiguously, you maximize spatial locality. This leads to fewer cache misses, shorter active CPU cycles, and—critically—less time spent driving the energy-intensive system bus to fetch data from slower main memory.
By aligning your data structures to match your access patterns, you stop wasting energy on "useless" data movement and keep the processor fed efficiently.
Key Takeaway: Improving spatial locality by restructuring data into contiguous blocks reduces bus traffic and minimizes the power-intensive latency cycles associated with cache misses.