In this lesson, you will learn how to achieve "dark silicon" in embedded designs by physically disconnecting entire power domains to eliminate leakage current in idle subsystems.
While techniques like peripheral clock gating (Lesson 20) prevent switching power by stopping the clock signal, they do nothing to mitigate the static leakage current inherent in CMOS transistors (Lesson 10). When a subsystem is not needed for extended periods, the most effective strategy is to cut its power supply rail entirely using a Power Management Unit (PMU) or an integrated Power Domain Controller.
The Mechanism of Power Gating
Power domains are physically isolated sections of the silicon die, each equipped with its own voltage rail. A "power switch"—typically a large, low-resistance MOSFET—is placed between the global power supply and the local domain's supply rail. When the control register is toggled, this switch opens, collapsing the voltage in that domain to zero.
Because the supply voltage is removed, the leakage current drops to near-zero, regardless of the input states of the gates within that domain.
Implementation Logic
To safely power down a block, the software must perform a sequence: save the critical state to non-volatile or "always-on" memory, isolate the signals at the interface boundary to prevent floating inputs (Lesson 24), and finally, trigger the power-off register.
// Example: Powering down a sub-block via the Power Control Register (PWR_CR)
void power_off_subsystem(uint32_t domain_mask) {
// 1. Isolate inputs to prevent leakage paths
ISOLATION_ENABLE |= domain_mask;
// 2. Disable the domain power switch
PWR_CR &= ~domain_mask;
// 3. Optional: Wait for power-down acknowledgement
while (!(PWR_SR & domain_mask));
}
When the subsystem is needed again, the controller reverses this process. Note that because the power is cut, the internal state (registers, flip-flops) of that subsystem is lost. You must treat this as a "hard" power-on event, requiring the peripheral to be reinitialized from scratch. This approach trades wake-up latency and state-retention complexity for the absolute minimum static power consumption possible in a CMOS system.
Key Takeaway: Power gating completely eliminates static leakage current in idle subsystems by physically disconnecting their supply voltage, though it requires careful state saving and full reinitialization upon wake-up.