Validating Interrupt Latency and Response Timing

In this lesson, you will learn how to design targeted hardware verification scenarios that prove your peripheral interrupt signals strictly adhere to the timing constraints required by your RTOS kernel.

When an interrupt occurs, the time between the physical signal assertion and the execution of the first instruction in your Interrupt Service Routine (ISR) is the "Latency Budget." If the hardware takes too long to signal or the kernel’s gating logic is misaligned, you risk missing real-time deadlines or triggering spurious error handlers.

The Verification Scenario

To validate this, you must treat the CPU-Interrupt controller interface as a black box with strict performance contracts. Instead of just observing logs, you should create a Hardware-in-the-loop (HIL) scenario that measures the "Delta" between a stimulus and a response.

1. Stimulus: Use an FPGA or a logic analyzer with signal generation capabilities to toggle an interrupt line.
2. Instrumentation: Toggle a non-critical GPIO pin at the very first line of your ISR.
3. Measurement: Use an oscilloscope or a high-speed logic analyzer to capture the time difference ($\Delta t$) between the rising edge of the interrupt request and the rising edge of your ISR-triggered GPIO.

Code-Level Timing Probe

To isolate the latency, ensure your ISR is as lean as possible during testing:

void __attribute__((interrupt)) Timer_ISR(void) {
    // 1. Immediate hardware feedback
    *GPIO_LATENCY_PIN = 1; 

    // 2. Clear hardware flag to end the signaling phase
    *INT_CLEAR_REG = TIMER_INT_BIT;

    // 3. Perform actual work...
}

By comparing the measured $\Delta t$ against the latency limits defined in your system specification (e.g., < 5μs), you verify that the hardware integration is sound. If the jitter in $\Delta t$ is high, it suggests contention in the internal bus matrix or unexpected interrupt masking by the kernel's critical sections. This approach moves you from guessing why a system is sluggish to empirically proving that your interrupt controller meets the precise timing requirements of your software architecture.

Key Takeaway: Precise verification of interrupt latency requires measuring the delta between physical signal assertion and a software-instrumented GPIO pulse to ensure the hardware-to-kernel handoff adheres to your timing budget.