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Lesson 599 of 9368. Advanced Debugging and Hardware VerificationFree lesson

Verifying PCB Connectivity with Boundary Scan

Learners will execute interconnect tests to detect open circuits and short circuits between components on a populated printed circuit board.

In this lesson, you will learn how to systematically identify electrical manufacturing faults—such as open pins or shorted traces—using the IEEE 1149.1 Boundary Scan architecture without physically probing the board.

The Concept of Interconnect Testing

When a board is populated, physical access to high-density BGA (Ball Grid Array) components is impossible with standard oscilloscope probes. Boundary Scan solves this by placing a "virtual" probe at every digital pin of a JTAG-compliant IC. By shifting patterns through the Boundary Scan Register (BSR), we can force signals onto output pins and capture them at input pins of adjacent components.

Detecting Faults

To verify connectivity, we shift a specific "walking" pattern (e.g., 0000, 0001, 0010, 0100, 1000) through the chain. By comparing the expected captured data against the actual data, we can isolate the failure:

  1. Open Circuit: If we drive a high signal (1) from a source pin but the destination pin reads a 0 (or floats to an indeterminate state), the trace is broken.
  2. Short Circuit: If we drive a 0 on one net and a 1 on another, but both destination pins read the same value (e.g., both read 1 or both read 0), the nets are physically bridged together on the PCB.

Execution Flow

The process typically follows these steps:

  1. EXTEST Instruction: Load the EXTEST instruction into the instruction register to allow the scan chain to control pin states.
  2. Shift-DR: Shift the stimulus vector into the boundary register of the driving component.
  3. Update-DR: Apply the stimulus to the physical pins.
  4. Capture-DR: Sample the state of the receiving pins.
  5. Shift-DR: Move the captured data out to the host controller to analyze the results.

This process essentially turns your entire PCB into a giant, non-intrusive logic analyzer, allowing you to map the physical integrity of your traces long before the board even boots its firmware.

Key Takeaway: By utilizing the EXTEST mode of the Boundary Scan chain, you can programmatically isolate manufacturing defects by comparing driven stimulus against captured responses, effectively turning inaccessible internal traces into observable test points.