Instruction Register and Data Register Chaining

In this lesson, you will learn how to coordinate the JTAG Instruction Register (IR) and Data Register (DR) to perform boundary scan operations, allowing you to observe and control the physical pins of an integrated circuit.

The Mechanism of Chaining

In the JTAG state machine, the Instruction Register and Data Register are not isolated silos; they function as a serial chain. When you initiate a boundary scan, the process follows a strict two-step "chaining" sequence.

1. Instruction Shift: You shift a specific command (such as SAMPLE or EXTEST) into the IR. This command essentially "configures" the internal multiplexers of the chip, telling it which DR to connect to the serial path (TDI to TDO).
2. Data Shift: Once the instruction is latched, you shift data into the selected DR. Because the DR is now "chained" between the TDI and TDO pins, every bit you shift in physically corresponds to a state on a specific I/O pin or a capture of that pin’s current voltage level.

Practical Illustration

Think of the IR as a railway switch that determines which track the data will travel on. By shifting 0x01 (a hypothetical EXTEST command) into the IR, you are essentially instructing the hardware to place the Boundary Scan Register (a type of DR) into the serial path.

// Conceptual pseudo-code for a boundary scan chain operation
jtag_state_transition(SHIFT_IR);
jtag_shift_bits(EXTEST_COMMAND, IR_LENGTH); // Configure the path

jtag_state_transition(SHIFT_DR);
jtag_shift_bits(input_pin_patterns, DR_LENGTH); // Control/Observe pins
jtag_state_transition(UPDATE_DR); // Apply the patterns to physical pins

When you perform the UPDATE_DR state transition, the bits you pushed into the DR are moved from the shift register to the output buffers of the pins themselves. This chaining allows you to bypass the chip’s core logic and manipulate the physical PCB traces directly. By chaining the registers, you transform a complex IC into a series of transparent digital switches, providing the ultimate visibility into board-level connectivity.

Key Takeaway: Instruction Register and Data Register chaining creates a serial pathway that allows you to configure internal hardware modes via the IR and then physically toggle or read external pins through the corresponding DR.