Measuring Interrupt Latency with Logic Analyzers

In this lesson, you will learn how to physically quantify the precise duration between an external interrupt signal and the first instruction of your Interrupt Service Routine (ISR) using a logic analyzer.

Understanding the Latency Gap

Interrupt latency is the interval between the hardware triggering an interrupt request (IRQ) and the execution of the first line of C code in your ISR. This delay includes hardware pipeline flushes, context saving (register stacking), and the vector fetch process. Because software-based profiling can interfere with the very timing it measures, using an external logic analyzer provides the most accurate, non-intrusive results.

Instrumentation Strategy

To capture this timing, you must map two distinct signals to your logic analyzer’s input channels:

1. Channel 0 (Trigger): The physical pin or signal line asserting the interrupt (e.g., an external GPIO interrupt or a peripheral interrupt request signal).
2. Channel 1 (Indicator): A "breadcrumb" GPIO toggle at the very start of your ISR.

By setting a GPIO high at the very first line of your ISR, you create a "hook" that the logic analyzer can capture.

void GPIO_ISR_Handler(void) {
    // Immediate toggle to signal execution start
    GPIO_PORT->DATA |= (1 << PIN_DEBUG); 
    
    // Original ISR logic follows
    Process_Interrupt_Data();
    
    GPIO_PORT->DATA &= ~(1 << PIN_DEBUG);
}

Capturing the Delta

Configure your logic analyzer to trigger on the falling (or rising, depending on your hardware) edge of the interrupt signal (Channel 0). Once the capture completes, use the measurement cursors to identify the elapsed time between the IRQ assertion and the rising edge of your debug GPIO on Channel 1.

If you notice excessive jitter or latency beyond your project's timing budget, this data confirms the bottleneck exists within the processor’s architecture (e.g., interrupt nesting depth or high-priority masking) rather than within your peripheral configuration. This physical measurement is the "ground truth" that validates your real-time system performance.

Key Takeaway: By correlating an external trigger signal with a software-triggered GPIO toggle, you can use a logic analyzer to measure the absolute hardware-to-software latency without introducing the timing artifacts inherent in software-based tracing.