In this lesson, you will learn how to architect JTAG scan chains to gain full visibility into the physical pins of your integrated circuits without ever needing a physical logic probe.
The Concept of Boundary Scan
Boundary Scan, defined by the IEEE 1149.1 standard, places a "boundary cell" between the internal logic of an IC and its external physical pins. When you architect a JTAG chain, you are effectively creating a virtual shift register that spans across all the pins of every component in the chain. By shifting data into this chain, you can force states onto pins (controlling outputs) or shift states out of the chain to read the actual logic levels present on the pins (observing inputs).
Architecting the Chain
To architect a robust scan chain, you must connect the devices in series. The TDO (Test Data Out) of the first device connects to the TDI (Test Data In) of the next. All devices share the same TCK (Test Clock) and TMS (Test Mode Select) lines.
Consider a system with a processor and a peripheral FPGA. To perform board-level interconnect testing, you would define the chain in your BSDL (Boundary Scan Description Language) files like this:
-- Logical representation of a two-device JTAG chain
attribute COMPONENT_CONFORMANCE of MyBoard : entity is "IDCODE";
attribute INSTRUCTION_LENGTH of Processor : entity is 5;
attribute INSTRUCTION_LENGTH of FPGA : entity is 10;
-- TDO of Processor connected to TDI of FPGA
-- Total Scan Chain Length = 5 + 10 = 15 bits
Practical Application
When you move the JTAG state machine into EXTEST mode, the system ignores the internal core logic. Instead, it uses the scan chain to capture the state of every board-level trace. This allows you to perform "connectivity testing"—checking for shorts, open circuits, or solder bridges between chips—without requiring expensive bed-of-nails fixtures or manual probing.
By strategically placing devices in the chain, you create a virtual "X-ray" of your PCB’s connectivity. If a signal isn't reaching its destination, the boundary scan chain will show you exactly where the logic level stopped, allowing you to isolate hardware faults in seconds.
Key Takeaway: Boundary scan transforms your JTAG chain into a virtual, non-intrusive test probe that grants you complete read/write control over every physical pin on your board.