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Lesson 313 of 9364. Peripheral Interfacing and ControlFree lesson

Architecture of Nested Vectored Interrupt Controllers

Learners will examine the internal structure of the NVIC to understand how hardware manages multiple concurrent interrupt requests and vector table lookups.

In this lesson, you will learn how the Nested Vectored Interrupt Controller (NVIC) acts as the traffic controller for your processor by prioritizing and managing simultaneous events.

The Role of the NVIC

In complex systems, multiple peripherals—like your PWM timers and ADC modules—might demand attention at the same time. Without a specialized controller, the CPU would have no way to decide which task is more urgent. The NVIC is a hardware block tightly integrated into the processor core that handles this congestion.

Handling Concurrent Requests

The "Nested" in NVIC is its most powerful feature. If a high-priority interrupt occurs while the CPU is already running a lower-priority interrupt handler, the NVIC can pause the current task, save the necessary state, and jump to the more urgent handler immediately. Once the urgent task completes, it "unwinds" and resumes the lower-priority work.

The NVIC manages this using a Vector Table. This is essentially a predefined list of memory addresses stored at the start of your program’s memory. When an interrupt signal arrives:

  1. The NVIC identifies the source.
  2. It fetches the corresponding address from the Vector Table.
  3. It forces the CPU to jump to that function (the Interrupt Service Routine, or ISR).

Hardware Prioritization

Every interrupt is assigned a priority level. If two interrupts trigger at once, the NVIC uses a hardware-based priority encoder to select the "winner."

// Conceptually, you configure the priority in NVIC registers:
NVIC_SetPriority(TIMER_IRQn, 1); // High priority
NVIC_SetPriority(ADC_IRQn, 2);   // Low priority

Because this lookup and priority decision happens in hardware logic gates rather than software, the latency—the time between the signal hitting the pin and your code executing—is deterministic and extremely fast. This is vital for systems like motor control, where missing an interrupt could result in a physical hardware failure or jittery PWM output. The NVIC doesn't just pass signals; it maps, ranks, and sequences them so your code doesn't have to guess who needs attention first.

Key Takeaway: The NVIC is a hardware-based arbiter that uses a prioritized Vector Table to manage concurrent interrupt requests, allowing high-priority events to preempt lower-priority tasks with minimal latency.