Synchronizing Multiple Timers for Complex Sequences

Learners will configure master-slave timer relationships to coordinate multi-channel output operations that require precise phase alignment across different hardware modules.

In this lesson, you will learn how to configure master-slave relationships between hardware timers to ensure perfectly aligned output sequences across multiple pins.

Why Coordinate Timers?

While a single timer is great for basic PWM, complex systems—like multi-phase motor control or synchronized LED arrays—often require multiple timers to work in lockstep. If you start two timers manually in code, their start times will be slightly skewed by the CPU's instruction execution timing. To achieve true hardware-level synchronization, we use a Master-Slave configuration.

The Master-Slave Architecture

In this setup, one timer acts as the "Master" and one or more others act as "Slaves." You configure the Master timer to export its internal clock or its "Enable" signal via a hardware trigger. The Slave timer is configured to listen for this signal, starting or resetting itself only when the Master signals it to do so.

Because this synchronization happens inside the silicon, there is zero latency between the Master’s trigger and the Slave’s response.

Implementation Concept

To set this up, you typically modify two specific registers:

Master Mode Register: Tell the Master timer to output a signal (like a reset or enable trigger) whenever it updates its counter.
Slave Mode Register: Tell the Slave timer to start counting or reset its counter only upon receiving the trigger from the Master.

// Conceptual configuration
// Configure Timer 1 as Master
Timer1->CR2 |= (0x02 << 4); // Set Master Mode: send Update event as Trigger

// Configure Timer 2 as Slave
Timer2->SMCR |= (0x04 << 0); // Select Trigger Input (ITR1 - connected to Timer 1)
Timer2->SMCR |= (0x06 << 0); // Set Slave Mode: Gated/Trigger mode

By linking these peripherals, you ensure that even if you have four different PWM channels spread across two physical timers, they will never drift apart. They effectively become a single, synchronized timing unit, allowing for phase-shifted signals that remain stable regardless of CPU load or interrupt activity.

Key Takeaway: By using hardware master-slave triggers, you eliminate software latency and achieve cycle-accurate synchronization between multiple timers.