In this lesson, you will learn how to manually pin hardware interrupt processing to specific CPU cores to minimize cache misses and reduce inter-processor latency.
The Mechanism of Interrupt Routing
When a hardware device (like a high-speed NIC or NVMe drive) triggers an interrupt, the kernel’s interrupt handler must execute to process the event. By default, the kernel distributes these interrupts across all available CPUs via the irqbalance daemon. While this ensures load balancing, it is often detrimental for performance-critical systems because it causes "cache thrashing." When an interrupt is handled by a CPU that does not currently store the relevant application data in its L1/L2 cache, the processor must fetch that data from memory, incurring a significant performance penalty.
Pinning via SMP Affinity
To optimize, we use SMP Affinity. Each interrupt has a mask defined in /proc/irq/[IRQ_NUMBER]/smp_affinity. This hexadecimal bitmask determines which CPUs are allowed to handle the interrupt.
For instance, if you have a 4-core system and you want to ensure your NIC (assigned to IRQ 45) is handled only by CPU 0, you would perform the following:
# Verify the current CPU mask
cat /proc/irq/45/smp_affinity
# Set the affinity to CPU 0 (hex mask 0x1)
echo 1 > /proc/irq/45/smp_affinity
Improving Cache Locality
By pinning an interrupt to a specific CPU core, you create a "warm" cache environment. If your application process is also pinned to that same core using taskset, the data arrives at the CPU, the interrupt triggers, and the user-space process resumes—all without the data ever leaving the local cache hierarchy.
This is particularly effective in NUMA systems, where you should route an interrupt to a CPU that resides on the same physical socket as the device's PCI bus. Routing an interrupt across NUMA nodes forces data to traverse the inter-connect bus (like QPI or UPI), which significantly increases latency and reduces memory throughput. Before applying these changes, ensure irqbalance is disabled, as it will periodically overwrite your manual affinity settings to re-balance the system.
Key Takeaway: By manually pinning interrupt affinity to specific cores, you eliminate cross-CPU data movement and maintain cache locality, drastically reducing latency for high-throughput hardware workloads.