In this lesson, you will learn how to quantify your system's ability to detect hardware faults by calculating Diagnostic Coverage (DC) metrics to meet strict safety integrity requirements.
Understanding Diagnostic Coverage
When designing high-integrity embedded systems, we assume that hardware components—like RAM, CPUs, or buses—will eventually fail. Diagnostic Coverage is a quantitative metric representing the effectiveness of your safety mechanisms. It is defined as the ratio between the failure rate of the detected dangerous failures and the total failure rate of dangerous failures.
If your Hazard Analysis (concept 24) dictates that a component must meet a specific Safety Integrity Level (SIL) or Automotive Safety Integrity Level (ASIL), you cannot rely on intuition. You must prove that your hardware monitors (like ECC, parity bits, or lockstep processors) are actually catching the faults.
Calculating the Metrics
The formula for the Diagnostic Coverage of a subsystem is:
DC = λ_detected_dangerous / λ_total_dangerous
For example, if a memory module has a total dangerous failure rate of 100 FIT (Failures In Time) and your parity check mechanism detects 90 of those, your DC is 90%. Standards like ISO 26262 provide specific tables for minimum DC levels required to achieve certain safety targets. If your DC is too low, you must implement additional redundancy or hardware monitors to "trap" the remaining 10% of failure modes.
Applying Hardware Monitors
Consider a simple parity check on a memory read operation:
// Hardware-assisted check logic
uint8_t read_data = peripheral->DATA_REG;
if (peripheral->STATUS & STATUS_PARITY_ERROR) {
// Diagnostic mechanism triggered:
// Increment 'detected_dangerous' counter for the FMEDA report
trigger_safe_state();
}
By integrating these metrics into your Failure Modes, Effects, and Diagnostic Analysis (FMEDA), you close the loop between your hardware design and your safety certification evidence. If your calculated DC does not meet the requirements defined in your safety plan, you must either improve the diagnostic mechanism (e.g., switching from simple parity to SECDED ECC) or reduce the failure rate of the component through hardware selection.
Key Takeaway: Diagnostic Coverage is the quantitative bridge between hardware reliability and safety certification, ensuring that your fault-detection mechanisms catch enough dangerous failure modes to meet your specified safety integrity targets.