Modeling System Failures with Fault Trees

In this lesson, you will learn how to build Fault Tree Analysis (FTA) diagrams to systematically map how low-level component faults aggregate into critical system-level failures.

The Logic of Failure

While watchdog timers or crash handlers are reactive, Fault Tree Analysis is a proactive, top-down deductive method. We start with an "Undesired Event" (the Top Event)—such as "System Unresponsive"—and work backward to identify the logical combinations of component failures that could cause it.

We use two primary logic gates to connect these events:

1. OR Gate: The system fails if any of the input events occur (e.g., a power supply failure OR a CPU thermal shutdown).
2. AND Gate: The system fails only if all input events occur simultaneously (e.g., the primary sensor fails AND the redundant backup sensor fails).

Practical Application: Autonomous Sensor Suite

Imagine we are analyzing an autonomous drone's "Loss of Attitude Control." We can model this using a tree:

• Top Event: Loss of Attitude Control
  • OR Gate:
    • Event A: Flight Controller Firmware Crash (e.g., Stack Overflow identified via our previous memory analysis techniques).
    • Event B: Sensor Data Corrupted
      • AND Gate:
        • Input 1: Primary IMU hardware failure.
        • Input 2: Backup IMU hardware failure.

By mapping this, we move beyond simple post-mortem debugging. We see that the firmware crash is a "Single Point of Failure" (SPF), while the sensor data loss requires a "Common Cause" or multiple distinct hardware faults.

Modeling for Reliability

When drafting your diagram, use standard symbols: rectangles for events, and circular symbols (OR/AND) for gates. In embedded systems, this helps quantify reliability. If you know the failure rate ($\lambda$) of your IMU, you can use the AND gate to calculate the probability of the redundant system failing: $P_{fail} = \lambda_{primary} \times \lambda_{backup}$.

This systematic approach allows you to justify adding hardware redundancy or implementing watchdog-based reset logic where the tree shows high sensitivity to single-point failures.

Key Takeaway: Fault Trees convert complex system dependencies into a logical visual map, allowing you to identify critical failure paths and design necessary hardware or firmware redundancies before a single line of code is deployed.