Data-Oriented Design Principles

In this lesson, you will learn how to refactor your application logic to align memory structures with CPU cache line expectations, moving away from object-oriented patterns that inhibit hardware efficiency.

In many architectural patterns, we model data as "objects" that contain both state and behavior (e.g., a Player struct with health, position, and inventory fields). While intuitive, this "Array of Structures" (AoS) approach causes the CPU to fetch unnecessary data into its cache. If you iterate through a thousand Player objects just to update their position, the CPU is forced to load their inventory and health fields into the L1 cache even though they aren't being used. This wastes precious bandwidth and increases cache misses.

Data-Oriented Design (DOD) flips this by using a "Structure of Arrays" (SoA) layout. By storing properties in contiguous, type-specific arrays, you ensure that the CPU prefetcher can stream relevant data into the cache with maximum density.

Consider this transition:

// AoS: Cache-inefficient for position updates
struct Player {
    position: [f32; 3],
    health: f32,
    inventory: Vec<Item>,
}

// SoA: Cache-efficient for position updates
struct World {
    positions: Vec<[f32; 3]>, // Iterating this is contiguous and cache-friendly
    healths: Vec<f32>,
    inventories: Vec<Vec<Item>>,
}

When your data is laid out this way, a loop updating all positions will consist of a simple, linear memory sweep. This allows the CPU to utilize SIMD (Single Instruction, Multiple Data) instructions effectively, as the data being processed is tightly packed without "holes" created by disparate fields.

To refactor your logic:

1. Identify the hottest loop in your system.
2. Extract only the fields strictly required by that loop.
3. Move those fields into a flat, contiguous vector.
4. Separate data from behavior, turning your "objects" into indices that look up properties in these dedicated buffers.

By prioritizing how the hardware accesses your memory rather than how you conceptually group your objects, you minimize latency caused by cache misses and maximize the throughput of your processing pipelines.

Key Takeaway: Prioritize contiguous, type-specific memory layouts to maximize cache line utilization and allow the CPU to perform linear, predictable data streaming.