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Lesson 1726 of 1,91015. Performance and Architectural EngineeringFree lesson

SIMD Vectorization Principles

Rewrite scalar mathematical loops to leverage parallel processing on single CPU cores.

In this lesson, you will learn how to transform scalar mathematical loops into parallelized operations that utilize Single Instruction, Multiple Data (SIMD) capabilities within your CPU.

The Scalar Bottleneck

When you process data in a standard Rust loop, the CPU executes one operation per cycle per element. For example, multiplying two arrays of f32 values a[i] * b[i] forces the processor to load, multiply, and store for every single index sequentially. This fails to utilize the wider execution units present in modern CPUs, which are capable of performing that same operation on 4, 8, or 16 elements simultaneously.

From Scalar to Vector

To move from scalar to SIMD, we shift our mindset from "processing an item" to "processing a lane." If your target architecture supports AVX-512, you can effectively treat your data as a single register containing 16 floats. Instead of:

// Scalar: One calculation at a time
for i in 0..data.len() {
    results[i] = a[i] * b[i];
}

We conceptually "widen" the loop body to operate on a Vec of elements. By restructuring your code to ensure data is aligned and stored in contiguous memory (leveraging the Structure-of-Arrays layout discussed earlier), you allow the compiler's auto-vectorizer to map these operations to vector registers.

Enabling the Transformation

The compiler can only vectorize loops that are "simple"—meaning no branching or complex dependency chains that would stall the pipeline. If your loop body contains a conditional if statement, you can often replace it with a mathematical equivalent (like using min or max intrinsics) to keep the pipeline straight.

By ensuring your data is not just contiguous but also memory-aligned to the register width (e.g., 32-byte alignment for AVX), you eliminate the need for expensive "masked" loads, allowing the CPU to execute the entire math operation in a single cycle.

Key Takeaway: SIMD vectorization transforms serial data processing into parallel lane operations by structuring your hot-path loops to be contiguous, branch-free, and memory-aligned, maximizing the throughput of your CPU’s execution units.