Concurrency and Cache Coherency

In this lesson, you will learn how to structure your Rust data to prevent "false sharing," a hidden performance killer in multi-threaded programs.

The Problem: Cache Lines and False Sharing

Modern CPUs don't fetch single bytes from memory; they fetch "cache lines" (typically 64 bytes). When your CPU modifies a piece of data, it marks that entire cache line as "modified." If another core is working on a different variable that happens to reside on that same cache line, the CPU hardware forces a cache coherency update. Even though the threads aren't actually sharing the same variable, the hardware thinks they are, forcing the cores to ping-pong the cache line back and forth. This is false sharing.

Structuring for Isolation

To fix this, you must ensure that frequently mutated variables used by different threads reside on different cache lines. You can achieve this in Rust using the #[repr(align(64))] attribute, which forces a type to start on a new cache line boundary.

Imagine two threads updating separate counters in a struct:

#[repr(align(64))]
struct PaddedCounter {
    value: std::sync::atomic::AtomicU64,
}

struct PerformanceCounters {
    // Each counter is guaranteed to occupy its own cache line
    counter_a: PaddedCounter,
    counter_b: PaddedCounter,
}

By wrapping your counters in a struct aligned to 64 bytes, you ensure that counter_a and counter_b cannot coexist on the same cache line. When Thread A increments counter_a and Thread B increments counter_b, the hardware no longer needs to synchronize the cache lines between cores.

Why this matters

Without the alignment, these two counters would likely sit right next to each other in memory. The moment Thread A writes to counter_a, the CPU invalidates the cache line for Thread B, forcing it to reload from main memory (or the L3 cache). By manually aligning your data, you convert a hardware-level synchronization bottleneck into true parallel execution.

Key Takeaway: Use #[repr(align(64))] to isolate hot, independently mutated data fields onto separate cache lines, effectively eliminating false sharing and reducing inter-core bus traffic.