In this lesson, you will learn how to improve system throughput and reduce latency by pinning network card hardware interrupts to specific CPU cores.
The Bottleneck of Default IRQ Handling
By default, the Linux kernel distributes hardware interrupts (IRQs) across all available CPU cores. For standard desktop workloads, this is fine. However, in high-performance network environments, this causes "cache thrashing." If a packet arrives and is processed by CPU 0, but the application consuming that packet is running on CPU 3, the CPU must constantly synchronize memory across caches, incurring a significant performance penalty.
By "tuning interrupt affinity," we force the kernel to handle specific network interface interrupts on a chosen set of cores. This ensures that the NIC, the kernel network stack, and your application all operate within the same CPU cache locality.
Implementing Affinity
First, identify which CPU cores are currently handling your network interface (usually eth0 or enpXsY) by examining the /proc/interrupts file:
grep eth0 /proc/interrupts
You will see a list of IRQ numbers associated with the interface. To pin a specific IRQ (e.g., IRQ 45) to a specific CPU, you modify its smp_affinity mask. The mask is a hexadecimal representation of the CPU cores. To pin IRQ 45 to CPU 2 (where 1 << 2 = 4 in hex), you run:
echo 4 > /proc/irq/45/smp_affinity
Best Practices for Throughput
If you have a multi-queue network card (RSS enabled), you will see multiple IRQs for the same interface. For optimal performance, you should spread these across the cores local to the NUMA node where the NIC is physically connected. Avoid pinning everything to CPU 0, as this can create a single-core bottleneck, effectively negating the benefits of your multi-core processor. Once you have pinned the interrupts, monitor the softirqs column in top to verify that the load is balanced according to your configuration.
Key Takeaway: Tuning interrupt affinity aligns network hardware processing with specific CPU cores to maximize cache hits and minimize inter-core synchronization latency.